The present invention relates to a semiconductor device, and more particularly, to a level shift circuit for converting an input signal having a first voltage level to an output signal having a second voltage level that is higher than the first voltage level.
Recent semiconductor devices (LSIs) are required to have an increased number of functions. This has lowered the power supply voltage and increased the number of power supplies in an LSI. In such an LSI, a level shift circuit is used as an interface circuit for connecting circuits having different power supply voltages.
FIG. 1 is a schematic circuit diagram of a level shift circuit described in Japanese Laid-Open Patent Publication No. 2002-190731. A level shift circuit 21 converts an input signal IN to an output signal OUT. The input signal IN shifts between a power supply voltage VD1 and ground voltage GND. The output signal OUT shifts between a power supply voltage VD2, which is higher than the power supply voltage VD1, and the ground voltage GND. The level shift circuit 21 includes an input circuit 22, a shift circuit 23, and a voltage generation circuit 24.
The input circuit 22 is an inverter circuit including a low breakdown voltage P-channel MOS transistor (PMOS transistor) Tr31 and a low breakdown voltage N-channel MOS transistor (NMOS transistor) Tr32. The input circuit 22 inverts the input signal IN to generate an inverted input signal /IN (‘/’ represents inversion).
The shift circuit 23 includes high breakdown voltage PMOS transistors Tr41 and Tr42, high breakdown voltage NMOS transistors Tr43 and Tr44, and low breakdown NMOS transistors Tr45 and Tr46. The gates of the NMOS transistors Tr43 and Tr44 in the shift circuit 23 are supplied with bias voltage VB from the voltage generation circuit 24. The gates of the NMOS transistors Tr45 and Tr46 are respectively supplied with the inverted input signal /IN and the input signal IN. The NMOS transistors Tr45 and Tr46 are activated and inactivated in a complementary manner in response to the inverted input signal /IN and the input signal IN. The output signal OUT is generated at a node between the drain of the PMOS transistor Tr41 and the drain of the NMOS transistor Tr43.
The voltage generation circuit 24 includes high breakdown voltage PMOS transistors Tr51, Tr52, Tr53, Tr54, Tr55, and Tr56 and high breakdown voltage NMOS transistors Tr57 and Tr58. The PMOS transistor Tr51 and the NMOS transistor Tr57 are both activated in response to a control signal CNTL having a high level. This generates a bias voltage VB of approximately ½×VD2 at a node between the drain of the PMOS transistor Tr53 and the source of the PMOS transistor Tr54.
In the level shift circuit 21, low breakdown voltage devices are used as the NMOS transistors Tr45 and Tr46 of the shift circuit 23. This ensures the activation and inactivation response of the transistors Tr45 and Tr46 with respect to the input signal IN. Further, high breakdown voltage devices are used as the NMOS transistors Tr43 and Tr44 of the shift circuit 23, and the bias voltage VB generated by the voltage generation circuit 24 is applied to the gates of the NMOS transistors Tr43 and Tr44. This prevents a voltage that exceeds the source-drain breakdown voltage of the low breakdown voltage NMOS transistors Tr45 and Tr46 from being applied to the drains of the transistors Tr45 and Tr46 (nodes Na and Nb).